In mid-May, Samsung said it had made a breakthrough in the 3nm chip manufacturing process and sent the chip design kit to potential customers. Thus, just a short time after 7nm chip became popular with mobile devices, and when the 5nm chip is still not available, Samsung has prepared a 3nm chip in 2021.
Even at the time when people thought Moore's Law had reached its limit, the industry still maintained its strong growth rate. But when the 3nm chip is about to come out and with the current shrinking chip size, can we have CPUs using 1nm process chips?
But maybe we should first understand what is the chip process?
Chip technology, or process or node, often refers to a specific process for producing semiconductors and its design rules. Different processes (or different nodes) often involve different circuit and architecture chip generations. Often, the smaller the technological process, the smaller the size of the chip (feature size), and the smaller the transistors, the faster and the more energy efficient. than.
Historically, the technological process is often related to a number of different sizes on transistors, including the gate length – the distance between the source and the trough on the transistor. This is the source of the processes with names like the 180nm, 110nm, 65nm or 45nm processes. The smaller the number, the smaller the distance, the smaller the transistor, the faster the chip.
If the process name previously represents the port length (distance from the source pole to the extreme drain), now this number is only meaningful, not any specific size.
However, starting from the 45nm process, Intel introduced a 25nm-sized port length on flat transistors. From this point on, further narrowing this gap will cause unexpected consequences. Along with Intel's introduction of a FinFET chip from the 22nm process, while other dimensions decrease, transistor density continues to increase, the gate length is almost constant, even increasing.
At this point, the name of each process is still the nanometer size, but it no longer represents or represents any size on the transistor. Numbers like 16nm, 10nm or 7nm mean only the names of processes and marketing for the capacity of chip manufacturers more than a certain size.
So the 1nm process chip could come in the future?
With names like the 10nm, 7nm or 3nm process only meaning, instead of some actual size of the transistor, so technically, 1nm process chips It is possible.
In particular, the process of chip processes under 3nm is also described in the ITRS International Semiconductor Technology Roadmap version 2.0 – a set of materials created by leading experts in the semiconductor industry. According to the latest version of this kit, processes smaller than 3nm will be 2.5nm and 1.5nm, expected to be released in the years 2027 and 2030. However, all are still predictions, because there are still other technical obstacles.
With FinFET chips, manufacturers' efforts are focused on narrowing the gap between the fin pitch, the width of each fin (fin width) and increasing their height (height fin).
It should be noted that, while the gate length is no longer narrowed, other sizes of transistors continue to be narrowed. With FinFET chips, semiconductor manufacturers focus on narrowing each fin's base (or chip fin), the distance between them and making them higher. The ultimate goal is to narrow down the transistor size.
However, to the current processes, chip manufacturing technologies have shown their shortness. Since switching to 22nm / 20nm chips, semiconductor manufacturers have used 193nm (193nm immersion lithography) embedded photolithography, but this technique has reached its limit when only the The engraving line is 40nm or more, so many chip makers are turning to another technique when it comes to chips with smaller processes.
In order to use EUV beams to make chips, it is necessary to have a near-absolute vacuum environment, so such ASML fabrication machines become very necessary for chip manufacturers.
That's why many chip makers, though still using 193nm photolithography to produce 10nm chips, like Intel and TSMC, have all begun to switch to EUV ultraviolet technology, with the ability to create The engraving line is only 13.5nm in size, to produce 10nm chips with better quality.
Switching to lower processes may require new replacement chip designs for FinFET, such as GAAFET and then MBCFET.
However, EUV photolithography can also be suitable only for 7nm and 5nm processes, down to processes less than 3nm, chip manufacturers will need new generation EUV photolithography technology called EUV. High aperture (High-Numerical Aperture EUV). Not only that, in these small processes, FinFET chip will no longer be suitable, but it can be replaced by GAAFETs to increase the number of transistors.
However, this is only a technical challenge in mass production of chips, and in the lab production, in 2016, researchers at Lawrence Berkeley Lab also created Transistors with a length of only 1nm – are much smaller than the chip size according to ITRS route. However, researchers use new materials such as carbon nanotubes and Molybden di-Sulfide compounds, so it will take a long time to go into mass production.
The 1nm transistor has appeared in the lab, but to launch a chip with such transistors will take a long time.
Not only technical challenges, another barrier that could prevent 1nm process processors from being released is actually an economic factor. The cost of developing chips with smaller processes has skyrocketed recently, and therefore only large companies can afford to design chips on these processes, like Intel. , AMD, Qualcomm or Apple, Samsung.
Expected development cost of 5nm chip will be nearly twice as high as 7nm chip and 3 times higher than 10nm chip.
While the cost of chip development is increasing at the current rate, the cost of manufacturing chips also increases with every move to a new process, maybe at some point, even Intel will stop creating. Smaller transistors. Therefore, many predict that 3nm may be the final limit of this process.
However, with the ITRS route set for processes of 2.5nm and 1.5nm in the years 2027 and 2030, we may have to wait a long time to answer these questions about the limits of Moore's law.